1. Field of Invention
The present invention relates to a method for manufacturing a shallow trench isolation structure. More particularly, the present invention relates to a method that utilizes a self-aligned mask for fabricating shallow trench isolation structure.
2. Description of Related Art
Chemical-mechanical polishing (CMP) is a global planarization technique for planarizing the surface of very-large scale integrated (VLSI) circuits or the more compact ultra-large scale integrated (ULSI) circuits. As the feature size of integrated circuits continues to decrease, CMP technique may become the only cost effective means of providing a planarized surface.
Size of semiconductor devices is constantly being reduced. Nowadays, semiconductor industry is fabricating deep sub-half micron devices having a line width of from 0.25 .mu.m down to about 0.18 .mu.m. The CMP technique has become an important surface planarization technique especially for planarizing the insulation layer within a shallow trench. However, dishing on the upper surface of a polished insulation layer may occur when the insulation layer is embedded within a wide trench area. Therefore, a reverse tone mask is sometimes formed over the insulation layer, and then the insulation layer is etched back to form an insulation layer having an undulating profile.
Subsequently, the reverse tone mask is removed and then the undulating insulation layer is polished using CMP technique to form a surface with a high degree of uniformity. However, should some misalignment of the reverse tone mask occur, a portion of the trench isolation structure may be etched away causing some structural damages.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps according to a conventional method for fabricating a shallow trench isolation structure using a reverse tone mask. First, as shown in FIG. 1A, a semiconductor substrate 10 is provided. Thereafter, a silicon nitride layer 12 is deposited over the substrate 10. Next, photolithographic and anisotropic etching operations of the silicon nitride layer 12 and the substrate 10 are carried out to form shallow trenches 14 between active regions 16.
In the subsequent step, as shown in FIG. 1B, an insulation layer, for example, a silicon dioxide layer, is deposited over the substrate and fills the shallow trenches 14, using a chemical vapor deposition (CVD) method. Since the substrate 10 has a highly undulating cross-sectional profile due to those trenches 14, the deposited silicon dioxide layer 18 has a rugged contour. In other words, the upper surface of the silicon dioxide layer 18 has a highly rugged cross-sectional profile, as well. Henceforth, a photoresist layer is deposited over the silicon dioxide layer 18, and then a photolithographic process is conducted to form a reverse tone mask 20. The reverse tone mask 20 is formed directly on top of the shallow trenches 14 just complementary to the active regions 16.
However, manufacturing errors may lead to a misalignment of the reverse tone mask 20, and hence the reverse tone mask may not cover the shallow trenches 14 entirely. Consequently, a portion of the silicon dioxide layer 18 may be exposed. When the silicon dioxide layer 18 is later etched, a portion of silicon dioxide layer 18 within the shallow trenches 14 will be removed forming recess cavities. These recess cavities may produce kink effect leading to short-circuiting or a leakage current. Furthermore, relying on a reverse tone mask to form a highly planar surface requires an additional mask-making operation, which will complicate the manufacturing process and increase the cost of forming the shallow trench isolation structure.
Next, as shown in FIG. 1C, the exposed silicon dioxide layer 18 is etched, and then the reverse tone mask 20 is removed. Therefore, grooves (unlabeled) are formed above the active regions 16 resulting in the formation of an undulating silicon dioxide layer 18a.
Finally, as shown in FIG. 1D, a portion of the silicon dioxide layer 18a that lies above the shallow trench 14 surface is removed using a chemical-mechanical polishing method. The polishing operation is conducted using the silicon nitride layer 12 as a polishing stop layer so that ultimately the upper surface of both the silicon nitride layer 12 and the insulation layer 18b are at the same level.
In light of the foregoing, there is a need to improve the method of fabricating shallow trench isolation structure.